The invention of the instant application is related to U.S. patent applications Ser. Nos. 08/276,131 (abandoned); 08/572,284; and 08/338,991 (allowed). The advent of heterostructure semiconductor devices has lead to the ease in fabrication and improved characteristics of many types of semiconductor devices. The light emitting diode (LED) the subject of the present invention, is an example of a device that benefits greatly from the use of heterostructure device design. Generally, the heterostructure employed in the fabrication of an LED is a double heterostructure, in which an active region III-V semiconductor (ternary or quaternary) is sandwiched between two oppositely doped III-IV compounds. By choosing appropriate materials of the outer layers, the band gaps are made to be larger than that of the active layer. This procedure, well known to the skilled artisan, produces a device that permits light emission due to recombination in the active region, but prevents the flow of electrons or holes between the active layer and the higher band gap sandwiching layers due to the differences between the conduction band energies and the valence band energies, respectively. An example of this is shown in FIG. 1, which is an energy band diagram of an N-n-P (where N,P are indicative of materials with greater band gaps than the n-doped active region) double semiconductor heterostructure, which shows the discontinuities 2,3 in energy levels of the conduction band energy (E.sub.c) and the valence band energy (E.sub.v) at the depletion regions that create the confinement of electrons and holes in the active region 1 (The Fermi level E.sub.f, is aligned at all three materials). The minority carrier concentration (holes) in the sandwiched region can have a magnitude comparable to the majority carrier concentration in the p-doped region. Accordingly, upon application of a junction forward bias, recombination takes place in and is essentially restricted to the central region, a feature of great advantage in the LED. A further advantage stems from a structure such as that shown, is that the dielectric constant of the higher bandgap layers is lower than that of the central lower bandgap region. Accordingly, the index of refraction of the lower bandgap region is higher than that of the lower bandgap regions, and a natural dielectric slab (assuming a rectangular layer structure) waveguide is formed.
Light emitting devices can be fabricated to emit light from an edge of the active layer, or as stated above, from a surface. The devices can be either light emitting diodes or lasers. For the purposes of clarity of instruction, one particular design will be described in detail. The particular design shows an edge emitting LED on an n-type substrate. However the same principles apply for these light emitting devices on a p-type substrate. Furthermore, the active layer composition for the these devices can be either of conventional bulk material or strained or unstrained quantum well type material. An Edge Emitting Light Emitting Diode (ELED), fabricated by conventional techniques is shown in FIGS. 2-4. Turning first to FIG. 2, a p-type indium phosphide (p-InP) layer 22 is grown on substrate 21. An n-InP cladding layer 23 is grown on the layer 22, and a v-groove is etched as shown with an active region of InGaAsP grown thereafter. Then, a p-cladding layer of InP 24 followed by a p.sup.+ layer of InGaAsP contact 25 or cap layer. Then a metal contact layer 26 is deposited on layer 25. With the exception of the metal contact layer 26, these layers are grown on the substrate epitaxially. In the structure as shown, distinct advantages are realized. First, as with other conventional devices, the natural waveguide is formed by choosing the appropriate cladding and active layers. Also, a buried structure is formed which enables current confinement which results in a lower current threshold level, and reduced operating temperatures. This current confinement comes about by selective junction biasing. To be specific to the example shown, a forward bias at the active/cladding region results in emission through recombination. However, as can be appreciated, application of an electric potential to effect a forward bias from active to cladding will result in a reverse bias in the lateral pn junctions, thus electrically burying the active region and resulting in current confinement. Optical confinement is also effected by the fact that the lateral regions are of lower index of refraction than that of the active region, resulting in a guided optical wave. FIG. 3 shows a p-type substrate of InP 31 having a buried crescent active region of p-GainAsP 33 and cladding layers of n-InP 32 and p-InP 34 respectively. In the particular device shown, there is shown the interface of the cladding and substrate regions at 36 which is angled to reduce reflections thereby reducing the probability of lasing. In a device designed to be an LED, it is undesirable to have a resonant cavity capable of supporting lasing action, and this is one method used to prevent this. The blocking layer is shown as an n InP layer 37, a p In-P layer 38 and an n InP layer 39. Finally, turning to FIG. 4, the basic structure as shown in FIG. 3 is found, however, a thyristor blocking region 47 is shown that separates the active region 43 from an absorption region of material identical to that of the active region. A substrate of p-InP 41, has a layer 46 n-InP 42 grown on top and a layer of p-InP 46 layer grown on top of layer 42. The lower cladding region is shown as p-InP 44, and an upper cladding region of n-InP is shown at 40. Furthermore, a layer of p-InGaAsP 48 is identical to the active layer 43. In purpose and effect, such a structure is designed to absorb any light that is refracted at the interface 46 and propagates through the thyristor blocking layer 47. Potentially, this could effect resonating and thereby result in undesired lasing. The device shown in FIG. 4 also has a dielectric cap of SiO.sub.2 which is supposed to reduce leakage current in the absorption region from the ohmic metal contact for the device which is deposited onto the top surface. The shortcoming of this approach is that there is still current leakage through the heavily doped cap layer of n-InGaAsP. This leakage current will result in electrical pumping of the absorption region of the LED, and accordingly, lasing effects could result. In addition, this leakage current (current flow from the absorption region) reduces the actual current needed to pump the active region. Furthermore, this structure, while effective in DC applications has great shortcomings in the ever increasing switching speeds required for example in communications applications. This is due to intrinsic capacitance between the layers that make up the device. Furthermore, the layer of dielectric which is used to decrease leakage current has the adverse affect of preventing heat dissipation as well as increasing device capacitance. It is desirable to reduce the area of the layers which reduces the capacitance, as well as to increase the ability to dissipate joule heating of the device.
With the desire for higher switching speeds, particularly the desire to reduce the rise and fall times of a digital optical signal, the ill-effects of parasitic capacitance must be reduced. Examples of attempts to curb the ill-effects of parasitic capacitance can be found in related U.S. Pat. Nos. 5,003,358; 5,100,833; 5,194,399 and 5,275,968 to Takahashi, et al. incorporated herein by reference. As is disclosed in the '358 reference, a semi-insulating or insulating substrate has deposited thereon a semi-insulating layer of InP which is etched to accommodate the p and n side electrodes as well as an vertical aperture in which an active layer is grown between p and n type cladding layers. Thereby, a light emitting device is formed in the aperture. Connecting the n-type cladding to the n side electrode is a conducting n-type InP layer which is buried in a groove etched in the semi-insulating layer. This structure having the light emitting device in a relatively small and confined region reduces the intrinsic parasitic capacitance by reducing the area of the p-n junctions of the device, and thereby the capacitance which is directly proportional to the area of the p-n junction. A good understanding of the ill-effects of this parasitic peripheral pn junction capacitance is found by a review of the prior art disclosed in FIG. 5 of the '358 reference. U.S. Pat. No. 5,309,467 to Terakado, the disclosure of which is specifically incorporated herein by reference, discloses a buried stripe semiconductor laser with a semi-insulating layer on either side of the buried mesa structure. This structure enables the operation of a laser with high luminous efficiency at elevated temperatures. This reference teaches the structure to effect lasing. What is desired is an LED which is capable of operating at high frequencies and at elevated temperatures.